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2148212

AI資料中心CXL記憶體擴展和池化基礎設施的市場規模、佔有率和成長預測（2026-2032年）

AI Data Center CXL Memory Expansion and Pooling Infrastructure Market Size, Share & Growth Forecast (2026-2032)

出版日期: 2026年09月24日 | 出版商:

Knowledge Sourcing Intelligence | 英文 148 Pages | 商品交期: 最快1-2個工作天內

價格

簡介目錄

2026 年，面向 AI 資料中心的 CXL 記憶體擴展和池化基礎設施市場規模估計為 12 億美元，預計到 2032 年將達到 68.3 億美元。這意味著從 2026 年到 2032 年的複合年成長率為 33.6%。

隨著運算密度不斷提升，傳統伺服器架構已無法有效率地提供足夠的記憶體容量和頻寬，人工智慧資料中心記憶體基礎設施市場正經歷結構性變革。計算快速連接（CXL）透過快取連貫協定擴展了PCIe的實體層，使處理器、加速器和記憶體設備能夠比傳統周邊設備更有效率地共用資料。因此，CXL不再只是伺服器的小眾增強功能，而是逐漸成為人工智慧基礎架構的基礎技術。推動這一市場發展的因素主要有三點：首先，基於代理的人工智慧和長上下文推理使得每個工作負載的記憶體使用量超過了本地加速器記憶體的經濟承受能力。其次，超大規模業者面臨DRAM容量與單一主機綁定，而工作負載需求卻不斷波動的問題。第三，向PCIe 6和CXL 3.2的過渡提升了外部記憶體鏈路的效能，使CXL連接的記憶體能夠滿足更廣泛的人工智慧工作負載的需求。北美地區憑藉其聚集的超大規模雲端服務供應商、人工智慧實驗室、CXL晶片供應商和記憶體系統新創公司，引領記憶體隔離架構的普及。亞太地區作為供應區域發揮關鍵作用，擁有三星電子、SK海力士、Montage Technology和Primemas等控制器開發商。歐洲則透過超大規模部署、高效能運算和半導體智慧財產權參與其中，而中東地區正在崛起為新興的需求區域，該地區新建的人工智慧園區可以採用記憶體隔離架構，而無需受限於傳統系統的兼容性。

市場促進因素

基於代理的人工智慧是目前最重要的需求推動要素。與傳統的短上下文推理相比，長上下文和多代理工作負載需要處理大量的模型狀態、鍵值快取和工作資料。將所有這些狀態儲存在高頻寬記憶體中成本高昂，並且會造成容量限制。重複將這些資料移至速度較慢的儲存設備會降低加速器的運轉率。 Astera Labs 將光纖連接記憶體定位為鍵值快取密集型工作負載的專用層，而 SK 海力士則展示了一種 CXL 池化記憶體系統，該系統可以在伺服器和圖形處理器之間重複使用鍵值快取。這使得 CXL 能夠在不限於傳統伺服器記憶體擴充的情況下，直接提升人工智慧效能。
CXL 技術提高了伺服器空閒記憶體的使用率。在傳統伺服器中，即使工作負載需求隨時間波動，DRAM 容量也綁定到單一主機。記憶體池化改變了這種模式，允許將機架級記憶體池分配給需要的主機。 Marvell、LIQID 和 Montage 等公司正著力推進動態分配和共用，以此減少過度配置並提高整個伺服器群的記憶體利用率。隨著 DRAM 容量的增加和營運商面臨記憶體供應短缺的問題，其經濟效益將更加顯著，因為避免閒置容量既能降低硬體成本，又能降低能耗。
PCIe 6 和 CXL 3.2 擴展了外部記憶體的可用頻寬。早期的 CXL 部署通常優先考慮容量，因為外部記憶體路徑比本地 DRAM 慢。過渡到 PCIe 6 和 CXL 3.2 將鏈路速度提升至每秒 64 GB，支援更高頻寬的控制器和交換器架構。 Astera Labs、Montage 和 Marvell 已於 2026 年發布或提供了 CXL 3.x 產品的樣品。鏈路效能的提升擴大了可使用 CXL 連接記憶體的工作負載範圍，而不會造成過多的延遲或頻寬損失。
機架級產品正在拓展CXL的應用範圍，使其不再侷限於單一擴充卡。商業系統正日益將眾多記憶體模組、CXL交換器和交換矩陣管理軟體整合到共用的機架級平台上。 LIQID銷售一種名為SmartStack的共享記憶體系統。 Primemas正在開發容量從數十Terabyte到超過Terabyte的JBOM系統。 CXL聯盟計劃在2026年舉辦的大型行業展會上展示機架級共享記憶體。這將目標市場從單純的半導體控制器擴展到完整的記憶體基礎設施系統及相關管理軟體。

市場限制因素

CXL 的普及仍然受到軟體成熟度、平台間互通性以及工作負載對延遲敏感度的限制。並非所有 AI 工作負載都能從大容量但速度較慢的記憶體層中獲益。軟體需要了解如何放置資料——高頻寬記憶體、本地 DRAM、CXL 記憶體和儲存。多主機池化也需要架構管理、作業系統支援和嚴格的故障隔離。超大規模雲端供應商可以開發自己的記憶體架構，從而限制了特定叢集中現成產品的商業機會。最後，經濟效益取決於記憶體價格。如果本地 DRAM 變得便宜且供應充足，一些擴展和池化項目可能不再具有吸引力的成本節約優勢。

促進因素
- 基於代理的人工智慧中記憶體使用量增加
- 閒置DRAM和記憶體利用率
- 透過 PCIe 6 和 CXL 3.2 擴展頻寬
- 機架級CXL系統的商業化
抑制因子
- 軟體和作業系統成熟度
- 延遲和工作負載放置敏感性
- 平台互通性和認證
- 面向超大規模的客製化記憶體架構

第11章競爭格局

市場結構與競爭強度
控制器和交換器平台的定位
記憶體製造商和模組生態系統
機架級資源池和組合式基礎架構基礎設施的策略
CPU、GPU 和超大規模生態系統領域的夥伴關係

第12章：公司簡介

Marvell Technology
Astera Labs
Montage Technology
SK hynix
Samsung Electronics
Micron Technology
LIQID
Primemas
Intel
AMD
NVIDIA
Microchip Technology
Cadence Design Systems
Synopsys
UnifabriX

第13章近期趨勢

第14章附錄

簡介目錄

Product Code: KSI-009253

The AI Data Center CXL Memory Expansion and Pooling Infrastructure Market is estimated at USD 1.20 billion in 2026 and is projected to reach USD 6.83 billion by 2032, representing a CAGR of 33.6% during 2026-2032.

The AI data center memory infrastructure market is undergoing a structural shift as compute density outpaces the ability of traditional server architectures to supply memory capacity and bandwidth efficiently. Compute Express Link, known as CXL, extends the PCIe physical layer with cache-coherent protocols that allow processors, accelerators and memory devices to share data more efficiently than conventional peripheral input and output. This positions CXL as a foundational technology for AI infrastructure rather than a niche server enhancement. The market is being propelled by three converging forces. First, agentic AI and long-context inference are expanding memory footprints per workload beyond what local accelerator memory can economically support. Second, hyperscale operators face growing volumes of stranded DRAM capacity that remains bound to individual hosts despite variable workload demand. Third, the transition to PCIe 6 and CXL 3.2 is raising external memory link performance to levels that make CXL-attached memory viable for a broader set of AI workloads. North America leads adoption because it concentrates hyperscale cloud providers, AI labs, CXL silicon vendors and memory-system startups. Asia Pacific functions as the primary supply region through Samsung Electronics, SK hynix and controller developers such as Montage Technology and Primemas. Europe participates through hyperscale deployments, high-performance computing and semiconductor intellectual property, while the Middle East emerges as a greenfield demand region where new AI campuses can adopt memory-disaggregated architectures without legacy compatibility constraints.

Market Drivers

Agentic AI is the single most important demand driver. Long-context and multi-agent workloads retain larger amounts of model state, key-value cache and working data than conventional short-context inference. Keeping all of this state in high-bandwidth memory is expensive and capacity constrained. Moving it repeatedly to slower storage reduces accelerator utilization. Astera Labs is positioning fabric-attached memory as a dedicated tier for key-value-cache-heavy workloads, while SK hynix has demonstrated CXL pooled-memory systems that reuse key-value cache across servers and graphics processors. This gives CXL a direct AI performance role rather than limiting it to conventional server memory expansion.
CXL improves utilization of stranded server memory. Traditional servers bind DRAM capacity to one host even when workload demand varies over time. Memory pooling changes that model by allowing a rack-level pool to be allocated to whichever host requires it. Marvell, LIQID and Montage all emphasize dynamic allocation or sharing as a way to reduce overprovisioning and increase fleet-level utilization. The economic benefit grows as DRAM capacity rises and operators face tighter memory supply, because avoiding idle capacity reduces both hardware cost and energy consumption.
PCIe 6 and CXL 3.2 increase the bandwidth available to external memory. Earlier CXL deployments were often capacity-oriented because the external memory path was slower than local DRAM. The transition to PCIe 6 and CXL 3.2 increases link speed to 64 gigatransfers per second and supports higher-bandwidth controller and switch architectures. Astera Labs, Montage and Marvell all introduced or sampled CXL 3.x products during 2026. Higher link performance expands the range of workloads that can use CXL-attached memory without excessive latency or bandwidth penalties.
Rack-scale products are moving CXL beyond individual add-in cards. Commercial systems increasingly integrate many memory modules, CXL switches and fabric-management software into shared rack-scale platforms. LIQID markets SmartStack pooled-memory systems. Primemas is developing JBOM systems reaching tens to more than 100 terabytes. The CXL Consortium highlighted rack-scale pooled-memory demonstrations at major industry events in 2026. This changes the addressable market from semiconductor controllers alone to complete memory-infrastructure systems and associated management software.

Market Restraints

CXL adoption remains constrained by software maturity, platform interoperability and workload sensitivity to latency. Not every AI workload benefits from a larger but slower memory tier. Software must understand where data should reside across high-bandwidth memory, local DRAM, CXL memory and storage. Multi-host pooling also requires fabric management, operating-system support and disciplined fault isolation. Hyperscale cloud providers can develop custom memory architectures, which limits merchant opportunity in selected fleets. Finally, the economics depend on memory pricing. If local DRAM becomes inexpensive and abundant, some expansion and pooling projects deliver less compelling savings.

Technology and Segment Insights

Memory-expansion controllers represent the largest dedicated CXL infrastructure revenue pool in 2026. These controllers are required inside Type 3 memory cards, EDSFF modules and expansion appliances. They manage protocol translation, memory channels, reliability functions, telemetry and security. Marvell Structera X, Astera Labs Leo and Montage MXC illustrate the increasingly competitive controller market across CXL 2.0 and CXL 3.2 generations.
CXL switches are expected to grow fastest through 2032 as deployments move from single-host expansion toward shared memory and rack-scale disaggregation. Switches create the fan-out, routing and dynamic allocation required for multi-host memory pools. Near-memory accelerators and full pooled-memory appliances also expand rapidly from a smaller base because they add processing, compression or software-defined resource management around the memory tier rather than simply exposing additional capacity.
Type 3 memory cards and EDSFF modules form a growing category with very strong growth, deployed to attach scalable CXL memory capacity to servers. Rack-scale pooled-memory appliances remain an emerging category with very fast growth, capable of provisioning tens to hundreds of terabytes across multiple hosts. Fabric-management software and services function as a supporting layer with very strong growth, enabling discovery, allocation, monitoring and orchestration of pooled memory.
On architecture, the market spans single-host memory expansion, multi-host memory sharing, dynamic capacity devices, rack-scale memory pooling and fabric-attached accelerator memory. Dynamic capacity devices represent a significant architectural advance. Montage has demonstrated live CXL 3.2 Dynamic Capacity Device operation across multiple hosts, validating the allocation and release of memory without server reset. By CXL generation, the market covers CXL 2.0, CXL 3.0 and 3.1, CXL 3.2, and the CXL 4.0 roadmap. CXL 4.0 increases signaling to 128 gigatransfers per second and continues the roadmap toward higher-bandwidth composable infrastructure.
By AI use case, the market serves agentic AI and long-context inference, key-value-cache and context-memory tiering, recommendation and in-memory analytics, scientific AI and high-performance computing, and general-purpose cloud memory expansion. By customer type, demand comes from hyperscale cloud providers, AI labs and model developers, neocloud and graphics-processor-cloud operators, high-performance computing and research infrastructure, and enterprise and sovereign AI programs.

Competitive and Strategic Outlook

The competitive landscape spans CXL controller and switch suppliers, memory manufacturers, system vendors and software-defined composable-infrastructure companies. Marvell has built a broad CXL portfolio across expansion controllers, near-memory accelerators and switches. It strengthened that position through the 2026 acquisition of XConn, which added production CXL switching silicon. Astera Labs competes strongly in hyperscale memory controllers and is extending its Leo product line into direct fabric-attached AI memory. Montage Technology is advancing CXL 3.2 controllers, retimers and dynamic-capacity implementations.
Memory manufacturers influence adoption because CXL devices ultimately depend on qualified DRAM and module designs. SK hynix is demonstrating pooled and compute-enabled CXL memory for AI. Samsung Electronics and Micron participate in module development, validation and large memory-system programs. Primemas is building high-capacity CXL memory systems with Micron and Samsung collaboration. LIQID combines CXL hardware with software-defined orchestration to deliver rack-scale pooling.
Competitive differentiation centers on CXL generation, bandwidth, memory-channel count, reliability and serviceability, security, platform interoperability, pooling features, fabric-management software and the ability to demonstrate measurable AI workload gains. The market is likely to favor vendors that can prove compatibility across central processing units, graphics processing units, memory suppliers and operating systems rather than isolated component performance.
Recent developments confirm accelerating commercialization. In September 2026, Astera Labs expanded its Leo Smart Memory Controller family with CXL 3.2 memory expansion and pooling products for agentic AI and hyperscale cloud workloads. Marvell demonstrated an end-to-end CXL memory architecture with Intel combining Structera X expansion, Structera S switching and PCIe and CXL retiming. Marvell also demonstrated Structera X interoperability with NVIDIA Vera, extending CXL expansion into next-generation AI central processing unit platforms. In August 2026, SK hynix demonstrated pooled-memory AI-agent serving and long-context inference using CXL memory. Primemas showcased a CXL full-stack portfolio and a 100-terabyte-class shared-memory architecture being developed with Micron for Pacific Northwest National Laboratory. In July 2026, Montage Technology announced trial production of a CXL 3.2 Memory eXpander Controller supporting PCIe 6.x, DDR5 and memory pooling. In March 2026, Marvell launched the 260-lane Structera S 30260 CXL switch for rack-level memory pooling. In February 2026, Marvell completed its acquisition of XConn Technologies.
In North America, the strongest near-term opportunity is capacity expansion and memory reuse. Hyperscale cloud fleets contain large volumes of servers where central processing unit performance remains adequate but memory capacity or bandwidth constrains deployment. CXL allows operators to add memory without replacing the complete host. New controller families support both DDR4 and DDR5 to improve utilization of installed memory inventory. This creates a commercial path before full rack-scale disaggregation becomes standard. Through 2032, North American growth is expected to shift progressively from individual expansion cards toward switched memory pools and fabric-attached accelerator memory.

Conclusion

The AI data center CXL memory expansion and pooling infrastructure market is positioned for rapid expansion, growing from USD 1.20 billion in 2026 to USD 6.83 billion by 2032 at a compound annual growth rate of 33.6 percent. The market is transitioning from component-level memory expansion toward rack-scale pooled memory and fabric-attached accelerator memory. Controllers represent the largest near-term revenue pool, while switches represent the fastest-growing hardware layer. Success will depend on software maturity, cross-platform interoperability and the ability to demonstrate measurable AI workload gains. Vendors that combine silicon performance with robust fabric-management software and broad ecosystem compatibility are best positioned to capture value as memory becomes an allocatable infrastructure resource rather than a fixed component of individual servers.

Key Benefits of this Report

Insightful Analysis: Detailed market insights across regions, customer segments, policies, socio-economic factors, consumer preferences, and industry verticals.
Competitive Landscape: Understand strategic moves by key players to identify optimal market entry approaches.
Market Drivers and Future Trends: Assess major growth forces and emerging developments shaping the market.
Actionable Recommendations: Support strategic decisions to unlock new revenue streams.
Caters to a Wide Audience: Suitable for startups, research institutions, consultants, SMEs, and large enterprises.

What Businesses Use Our Reports For

Industry and market insights, opportunity assessment, product demand forecasting, market entry strategy, geographical expansion, capital investment decisions, regulatory analysis, new product development, and competitive intelligence.

Report Coverage

Historical data from 2021 to 2024, Base year 2025, and Forecast years from 2026 to 2032
Growth opportunities, challenges, supply chain outlook, regulatory framework, and trend analysis
Competitive positioning, strategies, and market share evaluation, and trade analysis
Revenue growth and forecast assessment across segments and regions
Company profiling including strategies, products, financials, and key developments

1. Executive Summary

1.1. Market Opportunity and Key Findings
1.2. CXL Commercialization Outlook
1.3. Principal Revenue Pools

2. Market Overview

2.1. CXL Memory Architecture
2.2. Memory Expansion versus Sharing and Pooling
2.3. Type 3 Memory Devices and Dynamic Capacity
2.4. Fabric Management and Resource Allocation
2.5. CXL in AI Memory Hierarchies

3. Market Size and Forecast, 2026-2032

3.1. Global Market Revenue
3.2. Annual Growth Analysis
3.3. CXL-Attached Memory Capacity
3.4. Expansion versus Pooled-Memory Revenue

4. Market by Component

4.1. Memory-Expansion Controllers
4.2. CXL Switches
4.3. Type 3 Memory Cards and EDSFF Modules
4.4. Rack-Scale Pooled-Memory Appliances
4.5. Near-Memory Accelerators
4.6. CXL Retimers and Connectivity
4.7. Fabric-Management Software and Services

5. Market by Architecture

5.1. Single-Host Memory Expansion
5.2. Multi-Host Memory Sharing
5.3. Dynamic Capacity Devices
5.4. Rack-Scale Memory Pooling
5.5. Fabric-Attached Accelerator Memory

6. Market by CXL Generation

6.1. CXL 2.0
6.2. CXL 3.0 / 3.1
6.3. CXL 3.2
6.4. CXL 4.0 Roadmap

7. Market by AI Use Case

7.1. Agentic AI and Long-Context Inference
7.2. KV-Cache and Context-Memory Tiering
7.3. Recommendation and In-Memory Analytics
7.4. Scientific AI and HPC
7.5. General-Purpose Cloud Memory Expansion

8. Market by Customer Type

8.1. Hyperscale Cloud Providers
8.2. AI Labs and Model Developers
8.3. Neocloud and GPU-Cloud Operators
8.4. HPC and Research Infrastructure
8.5. Enterprise and Sovereign AI

9. Regional Market

9.1. North America
- 9.1.1. United States
- 9.1.2. Canada
9.2. Europe
9.3. Asia Pacific
9.4. Middle East and Rest of World

10. Market Dynamics

10.1. Drivers
- 10.1.1. Agentic AI Memory Footprint Growth
- 10.1.2. Stranded DRAM and Memory Utilization
- 10.1.3. PCIe 6 and CXL 3.2 Bandwidth Expansion
- 10.1.4. Rack-Scale CXL System Commercialization
10.2. Restraints
- 10.2.1. Software and Operating-System Maturity
- 10.2.2. Latency and Workload Placement Sensitivity
- 10.2.3. Platform Interoperability and Qualification
- 10.2.4. Hyperscale Custom Memory Architectures