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2148242

玻璃芯半導體基板市場規模、市佔率及成長預測（2026-2032 年）

Glass Core Semiconductor Substrates Market Size, Share & Growth Forecast 2026-2032

出版日期: 2026年09月28日 | 出版商:

Knowledge Sourcing Intelligence | 英文 150 Pages | 商品交期: 最快1-2個工作天內

價格

簡介目錄

預計到 2026 年，玻璃芯半導體基板市場規模將達到 1,200 萬美元，到 2032 年將達到 2.3 億美元。這意味著從 2026 年到 2032 年的複合年成長率將達到 63.6%。

構裝基板位於半導體封裝和印刷電路基板之間，負責傳輸電訊號和電力，同時提供機械支撐。在傳統的高性能基板中，通常使用有機多層材料來包裹有機芯材。隨著人工智慧 (AI) 封裝尺寸的增大，矽、有機材料和封裝結構之間熱膨脹係數的不匹配導致封裝在組裝和運行過程中容易發生翹曲。玻璃基板透過提供更高的剛性、更優異的尺寸穩定性以及更接近半導體材料的熱膨脹係數來解決這個問題。從電氣角度來看，玻璃基板的優勢同樣重要。更光滑、更穩定的芯材能夠提高層間對準精度，實現更精細的佈線，並透過玻璃通孔 (TGV) 實現高密度垂直連接。英特爾報告稱，與有機基板相比，玻璃基板能夠實現顯著更高的互連密度，從而實現更大外形規格的封裝。此外，玻璃基板還為嵌入被動元件、整合光學結構以及減少某些封裝架構所需的佈線層數提供了機會。商業化並非只是材料替換的問題。基板製造商需要掌握新的技術，包括玻璃處理、高精度通孔形成、籽晶層沉積、銅填充、線路重布、疊層、碎片處理和檢測。裂痕、邊緣損傷、金屬化層附著力、通孔缺陷和麵板處理等因素都會降低良率。因此，領先的供應商正在開發玻璃芯材，並結合金屬化、疊層工藝、檢測、封裝組裝和設計規範，而不僅僅是銷售未經處理的玻璃。

市場促進因素

人工智慧加速器封裝需要更大、更平整、更穩定的基板。人工智慧加速器擴大將大型邏輯晶片與多個高頻寬記憶體堆疊、晶片組和高速I/O介面整合在一起。因此，封裝面積遠大於傳統處理器封裝，互連數量也大幅增加。隨著封裝尺寸的增大，有機內核容易變形和翹曲，使得細間距組裝變得困難。玻璃基板能夠提供在大基板上保持對準所需的剛性和尺寸穩定性。這為採用玻璃基板提供了強力的理由，因為封裝良率和電氣性能的提升足以抵消製程複雜性增加帶來的額外成本。
晶片整合提高了佈線密度，並對封裝級互連提出了更高的要求。異質整合將許多系統級連接轉移到封裝內部。邏輯晶片、記憶體、加速器和專用 I/O 晶片需要在短距離和高密度連接下交換數據，同時也要獲得穩定的電源供應。玻璃芯可以在機械穩定的平台上支援精細佈線、高密度玻璃通孔結構和嵌入式組件。因此，這項技術可以彌補晶片架構的不足，否則晶片架構需要日益複雜的有機佈線堆疊和大型矽中介層。
面板級加工為大規模生產大型基板鋪平了道路。由於玻璃可以加工成大型矩形面板，因此在大面積構裝基板的製造方面具有潛在的優勢。面板級加工能夠提高單次加工的單元數量，並在良率達到商業性目標後減少材料浪費。 Absolics公司正在美國開發以面板為基礎的製造技術。亞洲的基板和材料製造商也在擴大其試生產和批量生產能力。經濟效益取決於處理自動化程度、通孔良率、金屬化均勻性和可拼接性是否能夠充分改進，從而滿足大規模生產的要求。
電源供應和高速訊號傳輸的需求往往促使人們傾向於選擇低損耗封裝平台。人工智慧和伺服器處理器需要在日益複雜的封裝中實現高電流供應和極高的資料傳輸速率。玻璃具有優異的電絕緣性和介電性能，其耐熱性進一步增強了封裝製程的柔軟性。英特爾也強調了在玻璃基封裝架構中整合電感器、電容器和光連接模組結構的潛力。這些特性拓展了玻璃封裝的價值提案，使其超越了機械翹曲控制的範疇，使其成為先進封裝協同設計的更廣泛平台。

市場限制因素

商業化面臨的限制因素並非技術興趣不足，而是製造技術的成熟度。玻璃通孔的形成需要高密度，同時避免開裂或造成不可接受的側壁損傷。銅金屬化層必須牢固地黏附在玻璃上。熱循環會在材料界面產生應力。大型面板還需要專門的搬運、偵測和裝框設備。這些挑戰會導致初始生產階段良率降低和成本增加。由於構裝基板必須在整個半導體組裝過程中滿足電氣、機械和熱可靠性要求，因此認證週期較長。有機基板也在不斷改進。要讓客戶重新設計現有的封裝平台，玻璃需要展現明顯的系統級優勢。

促進因素
- 大型人工智慧軟體包的翹曲和維度穩定性
- 晶片小型化和高密度互連
- 面板層面的製造業經濟學
- 電源和高速訊號要求
抑制因子
- TGV產量和玻璃破損風險
- 金屬化和介面可靠性
- 半導體認證週期很長。
- 有機基板的持續改進

第10章競爭格局

市場結構與技術成熟度
專業供應玻璃芯基板
構裝基板製造商的策略
特種玻璃和材料生態系統
關於設備、檢驗和流程的合作關係

第11章：公司簡介

Absolics
Intel
Samsung Electro-Mechanics
Toppan
AGC
Corning
SCHOTT
Nippon Electric Glass
Ibiden
Shinko Electric Industries
Unimicron Technology
Kinsus Interconnect Technology
AT&S
Resonac Holdings
Dai Nippon Printing

第12章近期趨勢

第13章附錄

簡介目錄

Product Code: KSI-009317

The Glass Core Semiconductor Substrates Market is estimated at USD 12.0 million in 2026 and is projected to reach USD 230.0 million by 2032, representing a CAGR of 63.6% across 2026-2032.

The package substrate sits between the semiconductor package and the printed circuit board. It carries electrical signals and power while providing mechanical support. Conventional high-end substrates typically use organic build-up materials around an organic core. As artificial intelligence packages become larger, the mismatch in thermal expansion between silicon, organic materials and the package structure can increase warpage during assembly and operation. Glass addresses this problem through higher stiffness, better dimensional stability and a coefficient of thermal expansion that can be engineered closer to semiconductor materials. The electrical case for glass is equally important. A smoother and more stable core can support tighter layer-to-layer registration, finer routing and dense vertical connections through through-glass vias. Intel has reported that glass substrates can provide substantially higher interconnect density than organic alternatives and enable larger form-factor packages. Glass also creates opportunities to embed passive components, integrate optical structures and reduce the number of routing layers required for selected package architectures. Commercialization is not a simple material substitution. Substrate manufacturers need new capabilities for glass handling, precision via formation, seed-layer deposition, copper filling, redistribution layers, build-up lamination, singulation and inspection. Cracking, edge damage, metallization adhesion, via defects and panel handling can reduce yield. The strongest suppliers are therefore developing the glass core together with metallization, build-up processes, inspection, package assembly and design rules rather than selling untreated glass alone.

Market Drivers

AI accelerator packages require larger, flatter and more stable substrates. Artificial intelligence accelerators increasingly combine large logic dies with multiple high-bandwidth memory stacks, chiplets and high-speed input and output interfaces. The resulting package area is substantially larger than a conventional processor package and the number of interconnections rises sharply. Organic cores can distort or warp as package dimensions increase, making fine-pitch assembly more difficult. Glass provides the rigidity and dimensional stability needed to preserve alignment across large substrates. This creates a strong adoption case where package yield and electrical performance justify the additional process complexity.
Chiplet integration increases routing density and package-level interconnect requirements. Heterogeneous integration shifts more system-level connectivity into the package. Logic chiplets, memory, accelerators and specialized input and output dies must exchange data across short, high-density connections while receiving stable power. Glass cores can support fine routing, dense through-glass via structures and embedded components within a mechanically stable platform. The technology therefore complements chiplet architectures that would otherwise require increasingly complex organic routing stacks or large silicon interposers.
Panel-level processing creates a pathway to scale large substrates. Glass can be processed in large rectangular panels, creating a potential manufacturing advantage for high-area package substrates. Panel-level processing can increase the number of units handled per process step and reduce material waste when yields reach commercial targets. Absolics is developing panel-based manufacturing in the United States. Asian substrate and materials companies are expanding pilot and production capabilities. The economic benefit depends on handling automation, via yield, metallization uniformity and singulation performance improving sufficiently for high-volume manufacturing.
Power delivery and high-speed signaling requirements favor low-loss package platforms. Artificial intelligence and server processors require high current delivery and very high data rates across increasingly complex packages. Glass offers favorable electrical insulation and dielectric characteristics. Its thermal tolerance enables additional package-process flexibility. Intel has also highlighted the potential to integrate inductors, capacitors and optical interconnect structures within glass-based package architectures. These capabilities expand the value proposition beyond mechanical warpage control and position glass as a broader platform for advanced package co-design.

Market Restraints

Commercial adoption is constrained by manufacturing maturity rather than lack of technical interest. Through-glass via formation must achieve high density without creating cracks or unacceptable sidewall damage. Copper metallization must adhere reliably to glass. Thermal cycling can introduce stress at material interfaces. Large panels also require specialized handling, inspection and singulation equipment. These challenges can create yield loss and increase cost during early production. Qualification cycles are long because package substrates must meet electrical, mechanical and thermal reliability requirements across the full semiconductor assembly process. Organic substrates also continue to improve. Glass must demonstrate a clear system-level advantage before customers redesign established package platforms.

Technology and Segment Insights

Glass-core flip-chip ball grid array and large advanced package substrates represent the primary commercialization path. They can replace the mechanically limiting organic core while retaining familiar build-up and assembly concepts. Through-glass via enabled structures provide vertical connectivity through the glass. Redistribution layers and dielectric build-up layers create the fine horizontal routing needed to connect chiplets and package terminals. Embedded-component glass substrates are a smaller emerging architecture that can integrate passive or active devices to shorten electrical paths and reduce package footprint.
Glass interposer structures remain an adjacent opportunity, particularly for radio-frequency, photonics and high-density heterogeneous integration. In these applications, glass can offer electrical isolation, low loss and dimensional stability while supporting through-glass vias. The distinction between a glass core package substrate and a glass interposer can narrow as package architectures incorporate multiple routing levels, embedded devices and optical functions within the same platform.
Artificial intelligence accelerators and high-performance computing are the leading commercial targets. These packages combine large area, dense interconnects and strong pressure to reduce power loss. Server central processing units and custom application-specific integrated circuits represent another important opportunity as chiplet designs expand. Radio-frequency and millimeter-wave systems can use glass for low-loss signal transmission and precise dimensional control. Co-packaged optics and photonic integration create a longer-term path where optical and electrical functions are brought closer to compute dies.
The market is segmented by package architecture, application, manufacturing technology, customer type and geography. Package architectures include glass-core flip-chip ball grid array substrates, through-glass via enabled glass core substrates, embedded-component glass substrates, and glass interposer and hybrid architectures. Applications include AI accelerators and GPUs, high-performance computing and server CPUs, custom ASICs and chiplet-based processors, RF and millimeter-wave devices, co-packaged optics and photonic integration, and other advanced semiconductor packages. Manufacturing technologies include glass panel preparation and handling, through-glass via formation, seed layer and copper metallization, redistribution layer formation, build-up dielectric and fine-line routing, and inspection, singulation and reliability testing. Customer types include integrated device manufacturers, fabless semiconductor companies, foundries and advanced packaging providers, package substrate manufacturers, and defense and high-reliability electronics.
Initial volume adoption is expected after 2027 in high-performance computing applications. Through-glass via formation and metallization remain critical manufacturing yield and reliability challenges. Asia Pacific leads substrate manufacturing depth while North America anchors early commercialization programs. Glass enables larger package formats, tighter routing and improved dimensional stability for chiplets.

Competitive and Strategic Outlook

Competition is still defined by technology readiness, customer qualification and manufacturing yield rather than installed high-volume capacity. Absolics is one of the most advanced dedicated glass-substrate suppliers and is using its Georgia facility to move from pilot manufacturing toward commercialization. Intel is developing glass substrates as part of its advanced packaging roadmap, focusing on future large-package and high-density computing applications. Samsung Electro-Mechanics is building an integrated glass-core and package-substrate capability and has publicly indicated mass-production plans after 2027.
Toppan participates through next-generation package substrates and glass interposer technologies. Specialty glass suppliers such as AGC, Corning, SCHOTT and Nippon Electric Glass provide material capabilities relevant to substrate flatness, thermal expansion, panel processing and high-frequency performance. Established package-substrate companies including Ibiden, Shinko Electric Industries, Unimicron, Kinsus and AT&S represent potential manufacturing participants as customer demand shifts from organic cores toward hybrid or glass-core platforms.
Competitive differentiation depends on more than the glass material. Suppliers must control via quality, metallization, fine-line redistribution, build-up adhesion, panel warpage, crack prevention, electrical inspection and package reliability. Companies that can provide design support and co-qualification with advanced packaging customers are likely to gain an advantage during the first commercial programs.
Asia Pacific has the deepest manufacturing ecosystem for glass core semiconductor substrates. The region combines advanced package-substrate suppliers, specialty glass producers, materials companies, semiconductor assembly providers and major artificial intelligence hardware customers. South Korea is emerging as a central commercialization hub. Samsung Electro-Mechanics operates a pilot line for glass package substrates and is building a glass-core supply structure with Sumitomo Chemical Group and Dongwoo Fine-Chem. SKC continues to fund Absolics and related glass-substrate development. The region also benefits from established flip-chip ball grid array manufacturing, build-up materials, plating chemistry, precision equipment and substrate inspection capabilities.
Japan contributes specialty glass, materials and substrate-processing expertise. Toppan is developing glass-core flip-chip ball grid array substrates and glass interposers. Companies across the Japanese materials ecosystem supply glass formulations, photoresists, build-up films, plating materials and precision processing equipment. Taiwan remains important through its concentration of advanced packaging, foundry and artificial intelligence accelerator production. This creates a natural qualification environment for glass substrate technologies once commercial volumes become available.
The region also benefits from close proximity between substrate manufacturers and package customers. Glass core adoption requires repeated co-development around design rules, through-glass via pitch, build-up stack, warpage, assembly temperature and package reliability. Locating pilot and production capability close to semiconductor packaging operations can reduce qualification time. This favors Asian manufacturing clusters during the early ramp even as U.S. policy support increases domestic capacity.
North America is the strongest early technology-development and strategic-investment region through Intel and Absolics. Intel has developed glass substrate technology at its advanced packaging operations in Arizona. Absolics operates its Covington, Georgia facility with federal support. Europe participates mainly through specialty glass, materials, precision equipment and research capabilities rather than large-volume package-substrate production.
Recent developments confirm accelerating market activity. In September 2026, Samsung Electro-Mechanics showcased glass substrates and related package technologies for AI accelerators, servers and data-center applications at KPCA Show 2026. In September 2026, SKC approved an additional KRW 281 billion investment in Absolics to accelerate glass-substrate commercialization and reliability evaluation. In May 2026, SEMI and Global Net Corp. released a dedicated glass core substrate market and development report, projecting rapid growth after 2028. In February 2026, SKC announced a KRW 1 trillion rights issue, with approximately KRW 590 billion allocated to Absolics product development. In July 2026, Samsung Electro-Mechanics and Sumitomo Chemical Group signed an agreement to establish a glass-core manufacturing joint venture and target mass production after 2027. In 2025, U.S. CHIPS program support for Absolics expanded the domestic glass-core packaging research, manufacturing and supplier ecosystem in Georgia.

Conclusion

The glass core semiconductor substrates market is at an early commercialization stage with very high growth potential. Growth is driven by AI package warpage limits, chiplet interconnect scaling, panel-level manufacturing economics and power delivery requirements. Initial volume adoption is expected after 2027 in high-performance computing. Through-glass via yield, metallization reliability and long qualification cycles remain the key restraints. Asia Pacific leads manufacturing depth, while North America anchors early commercialization. The market is projected to grow from USD 12.0 million in 2026 to USD 230.0 million by 2032 at a CAGR of 63.6%.

Key Benefits of this Report

Insightful Analysis: Detailed market insights across regions, customer segments, policies, socio-economic factors, consumer preferences, and industry verticals.
Competitive Landscape: Understand strategic moves by key players to identify optimal market entry approaches.
Market Drivers and Future Trends: Assess major growth forces and emerging developments shaping the market.
Actionable Recommendations: Support strategic decisions to unlock new revenue streams.
Caters to a Wide Audience: Suitable for startups, research institutions, consultants, SMEs, and large enterprises.

What Businesses Use Our Reports For

Industry and market insights, opportunity assessment, product demand forecasting, market entry strategy, geographical expansion, capital investment decisions, regulatory analysis, new product development, and competitive intelligence.

Report Coverage

Historical data from 2021 to 2024, Base year 2025, and Forecast years from 2026 to 2032
Growth opportunities, challenges, supply chain outlook, regulatory framework, and trend analysis
Competitive positioning, strategies, and market share evaluation, and trade analysis
Revenue growth and forecast assessment across segments and regions
Company profiling including strategies, products, financials, and key developments

1. Executive Summary

1.1. Market Opportunity and Key Findings
1.2. Commercialization Timeline
1.3. Technology Readiness and Adoption Outlook

2. Market Overview

2.1. Role of the Package Core in Advanced Semiconductor Packaging
2.2. Organic Core Limitations in Large AI Packages
2.3. Glass Material Properties and Package-Level Benefits
2.4. Through-Glass Via Architecture
2.5. Glass Handling, Metallization and Build-Up Integration

3. Market Size and Forecast, 2026-2032

3.1. Global Market Revenue
3.2. Commercialization Ramp and Volume Adoption
3.3. Pilot, Qualification and Production Transition

4. Market by Package Architecture

4.1. Glass-Core FC-BGA Substrates
4.2. TGV-Enabled Glass Core Substrates
4.3. Embedded-Component Glass Substrates
4.4. Glass Interposer and Hybrid Architectures

5. Market by Application

5.1. AI Accelerators and GPUs
5.2. High-Performance Computing and Server CPUs
5.3. Custom ASICs and Chiplet-Based Processors
5.4. RF and Millimeter-Wave Devices
5.5. Co-Packaged Optics and Photonic Integration
5.6. Other Advanced Semiconductor Packages

6. Manufacturing Technology

6.1. Glass Panel Preparation and Handling
6.2. Through-Glass Via Formation
6.3. Seed Layer and Copper Metallization
6.4. Redistribution Layer Formation
6.5. Build-Up Dielectric and Fine-Line Routing
6.6. Inspection, Singulation and Reliability Testing

7. Market by Customer Type

7.1. Integrated Device Manufacturers
7.2. Fabless Semiconductor Companies
7.3. Foundries and Advanced Packaging Providers
7.4. Package Substrate Manufacturers
7.5. Defense and High-Reliability Electronics

8. Regional Market

8.1. Asia Pacific
- 8.1.1. South Korea
- 8.1.2. Japan
- 8.1.3. Taiwan
- 8.1.4. China
8.2. North America
- 8.2.1. United States
8.3. Europe
8.4. Rest of World

9. Market Dynamics

9.1. Drivers
- 9.1.1. Large AI Package Warpage and Dimensional Stability
- 9.1.2. Chiplet and High-Density Interconnect Scaling
- 9.1.3. Panel-Level Manufacturing Economics
- 9.1.4. Power Delivery and High-Speed Signal Requirements
9.2. Restraints
- 9.2.1. TGV Yield and Glass-Cracking Risk
- 9.2.2. Metallization and Interface Reliability
- 9.2.3. Long Semiconductor Qualification Cycles
- 9.2.4. Continued Improvement in Organic Substrates