通用晶片互連標準 (UCIe) 市場規模、佔有率和成長預測 (2026–2032)

通用晶片互連標準 (UCIe) 市場預計在 2026 年達到 4 億美元，預計到 2032 年將達到 34 億美元。這意味著在預測期內，複合年成長率將達到 42.9%。

晶片組架構將傳統上整合到單一大型單晶片系統晶片(SoC) 中的功能拆分成更小的晶片，這些晶片可以單獨製造並整合到通用封裝中。這種方法可以提高良率、實現製程節點專業化，並重複使用成熟的智慧財產權 (IP)。然而，它也帶來了連接性問題。專有的晶片間介面在垂直整合的產品系列中運作良好，但卻難以整合來自不同供應商的晶片。 UCIe 透過定義通用的晶片間介面來解決這個問題。 UCIe 可以傳輸 PCI Express 和 Compute Express Link 等現有協議，並支援串流媒體和供應商自訂流量。商業機會不在於標準的所有權，而在於標準的實現。半導體設計人員需要實體層 IP、控制器、適配器邏輯、檢驗環境、封裝模型、訊號完整性分析、合規性測試和晶片偵錯功能。由於 UCIe 的效能取決於晶片電路和封裝通道，因此每個新的製程節點或封裝架構都會帶來額外的認證要求。標準封裝實現的目標是低成本的有機封裝。另一方面，先進的封裝實現方案透過採用細間距互連，顯著提高了頻寬密度。 UCIe 2.0 也引入了對3D封裝的支持，包括混合鍵結結構。 UCIe 3.0 將最大資料速率從 32 GT/s 提升至 64 GT/s。普及進程可能並不均衡。主要的雲端服務、處理器和加速器供應商無需等待開放市場建立，即可實現自己的晶片介面。當將第三方晶片整合到設計中，或需要向多個客戶提供可重複使用的晶片時，UCIe 的價值將更加凸顯。因此，在廣泛的商用晶片市場完全建立之前，介面 IP、檢驗和整合工具領域蘊藏著早期且最有前景的商業機會，這些工具能夠降低實現風險。

市場促進因素

• 人工智慧和高效能運算架構需要可擴展的晶片間頻寬。由於最先進的單片式晶片受到光罩尺寸、良率和成本的限制，人工智慧和高效能運算設備擴大採用多個運算、記憶體和I/O晶片。隨著封裝內晶片數量的增加，封裝內資料傳輸量急劇上升，互連功耗成為系統級的阻礙因素。 UCIe 3.0透過48 GT/s和64 GT/s的運行速度滿足了這一需求，同時保持了向後相容性。 Cadence和Synopsys已經在開發和流片64G級UCIe IP，這表明設計生態系統正在為大規模生產專案做準備，這些專案需要比第一代實現方案更高的頻寬密度。
• 開放介面降低了可重複使用、多廠商晶片平台的成本。當成熟的晶片可以在多個產品中重複使用，而不是為每個系統重新設計時，晶片就能帶來最大的經濟效益。標準化介面允許在最適合其各自功能的製程節點上開發計算、記憶體、射頻、安全或加速器晶片，並在封裝層級進行連接。 AMD 正在將此模式擴展到部分 Versal RF 系列裝置，其中 UCIe 允許在同一包裝內連接用於高頻轉換、人工智慧、中央處理器 (CPU)、圖形處理器 (GPU)、安全和特定應用功能的晶片。因此，隨著 UCIe 的普及，它可能會從單純的連接功能演變為平台實現的必要條件。
• 互通性測試正逐漸成為一項商業要求。即使有了既定的標準，獨立設計的晶片組也無法保證彼此無縫協作。 PHY 行為、訓練、邊帶訊號、封裝通道、錯誤處理和協定映射等都需要在不同廠商之間進行檢驗。英特爾和 Cadence 在 2026 年晶片峰會上進行的 UCIe-S 現場展示意義重大，因為它連接了獨立設計的晶片組，並在晶片層面檢驗了不同廠商之間的互通性。隨著更多供應商加入此生態系統，設計團隊將需要檢驗IP、合規性軟體、測試設備、協定分析以及系統化的互通性方案。這將使收入來源不再局限於介面 IP 本身。
• 3D封裝和新型應用類別正在拓展實現的可能性。 UCIe正在超越傳統的晶片並行排列方式。 UCIe 2.0引入了對3D封裝和細間距混合鍵合環境的支援。 UCIe 3.0增加了更高的資料速率、更長的邊帶傳輸距離和額外的管理功能。該聯盟也正在為汽車系統開發特定應用指南，因為可靠性、健康監測和長產品生命週期在這些系統中至關重要。這些增強功能將擴大介面IP、檢驗和測試解決方案的市場，涵蓋垂直堆疊、汽車運算、光晶片和其他異構系統。

市場限制因素

• 主要限制因素在於生態系的功能落後於規範的功能。多廠商晶片必須具備一致的電氣特性、封裝設計規則、散熱性能、安全前提條件、測試覆蓋率、韌體初始化以及供應鏈認證。因此，如果設計人員能夠控制封裝內的所有晶片，並且優先考慮最佳化而非互通性，他們可能會繼續使用專有的晶片介面。此外，在可重複使用晶片實現經濟效益之前，UCIe 的實施可能還需要額外的檢驗和合規性工作。先進的封裝方法需要精細間距組裝和高良率封裝。 3D3D進一步增加了溫度控管和測試的複雜性。因此，大規模生產中的應用很可能首先集中在那些整合成本可以透過晶片重用、外部採購或平台柔軟性來抵消的應用領域。

目錄

第1章執行摘要

• 市場機會與主要發現
• UCIe商業化的前景
• 建構開放的chiplet生態系統

第2章 市場概覽

• UCIe架構及其在多晶片系統中的作用
• 晶片間物理層和適配器架構
• 支援 PCI Express、Compute Express Link 和串流媒體協定。
• 標準和高級軟體包的實施
• UCIe 3D 和混合鍵結結構
• 互通性、可管理性和偵錯

第3章 市場規模及預測（2026-2032 年）

• 全球市場銷售
• 商業化和生產擴張
• 符合 UCIe 標準的設計程序的展望

第4章 市場：依實施層分類

• UCIe 控制器和協定 IP
• UCIe PHY IP
• 檢驗IP
• 設計、封裝和訊號完整性軟體
• 合規性和互通性測試系統
• 整合、推出和工程服務

第5章 市場：UCIe世代

• UCIe 1.x 實現
• UCIe 2.0 和 3D 包裝
• 實現 UCI 3.0 48G 和 64G
• 未來規格演變

第6章 市場：依包裝類型分類

• 標準軟體包 UCIe
• 進階 UCIe 包
• 2.5D中介層和橋接封裝
• 3D和混合鍵結多晶片系統

第7章 市場：依應用分類

• AI加速器與GPU
• 用於高效能運算和伺服器的CPU
• 資料中心網路和客製化雲端晶片
• 客戶端和邊緣運算
• 汽車計算
• 光學、記憶體和專用應用晶片

第8章 市場：依客戶類型分類

• 無晶圓廠半導體公司
• 垂直整合的設備製造商
• 面向雲端運算和超大規模應用的半導體開發公司
• 晶圓代工及先進封裝供應商
• 汽車和工業半導體製造商
• IP、EDA 和設計服務供應商

第9章：地方市場

• 北美洲
  • 美國
  • 加拿大
• 亞太地區
  • 台灣
  • 韓國
  • 日本
  • 中國和東南亞
• 歐洲
• 世界其他地區

第10章 市場動態

• 促進因素
  • 人工智慧和高效能運算中的晶片間頻寬需求
  • 可重複使用且與多廠商相容的晶片平台
  • 互通性和合規性要求
  • 3D包裝及新應用領域
• 抑制因子
  • 多個供應商的整合和認證的複雜性
  • 由於專有晶片間介面而導致的競爭
  • 先進封裝的良率與成本
  • 產品投產和規格製定方面的延誤

第11章 競爭格局

• 市場結構和商業化準備度
• 控制器和 PHY IP 競爭條件
• 檢驗和多晶片設計平台
• 合規性、測試和互通性生態系統
• 在晶圓代工和先進封裝領域建立合作夥伴關係

第12章：公司簡介

• Cadence Design Systems
• Synopsys
• Siemens EDA
• Intel
• AMD
• Qualcomm
• Arm
• NVIDIA
• Taiwan Semiconductor Manufacturing Company
• Samsung Electronics
• ASE Technology Holding
• Keysight Technologies
• Eliyan
• proteanTecs
• VeriSilicon

第13章 近期趨勢

第14章附錄

The Universal Chiplet Interconnect Express (UCIe) Market is estimated at USD 0.40 billion in 2026 and is projected to reach USD 3.40 billion by 2032, representing a CAGR of 42.9% during the forecast period.

Chiplet architectures divide functions that would traditionally reside on one large monolithic system-on-chip into smaller dies that can be manufactured separately and integrated within a common package. This approach can improve yield, allow process-node specialization and enable reuse of proven intellectual property. It also creates a connectivity problem. Proprietary die-to-die interfaces work well inside vertically integrated product families but make it difficult to combine dies from different suppliers. UCIe addresses this problem by defining a common die-to-die interface. It can transport established protocols such as PCI Express and Compute Express Link while also supporting streaming and vendor-defined traffic. The commercial opportunity sits around implementation rather than ownership of the standard. Semiconductor designers require physical-layer IP, controllers, adapter logic, verification environments, package models, signal-integrity analysis, compliance testing and silicon-debug capabilities. Each new process node and package architecture creates additional qualification requirements because UCIe performance depends on both die circuitry and the package channel. Standard-package implementations target lower-cost organic packages. Advanced-package implementations use fine-pitch interconnects to reach substantially higher bandwidth density. UCIe 2.0 also introduced support for three-dimensional packaging, including hybrid-bonded structures. UCIe 3.0 doubled the maximum data rate from 32 GT/s to 64 GT/s. Adoption is likely to progress unevenly. Large cloud, processor and accelerator vendors can deploy internal chiplet interfaces without waiting for an open marketplace. UCIe becomes more valuable when a design incorporates third-party chiplets or when a reusable die must serve several customers. The strongest early commercial opportunities therefore exist in interface IP, verification and integration tools that reduce implementation risk before a broad merchant chiplet marketplace is fully established.

Market Drivers

• AI and HPC architectures require scalable die-to-die bandwidth. Artificial intelligence and high-performance computing devices are increasingly built from multiple compute, memory and input and output dies because leading-edge monolithic chips face reticle-size, yield and cost constraints. As packages integrate more dies, the amount of data transferred inside the package rises sharply and interconnect power becomes a system-level limitation. UCIe 3.0 addresses this requirement with 48 GT/s and 64 GT/s operation while maintaining backward compatibility. Cadence and Synopsys are already developing and taping out 64G-class UCIe IP. This indicates that the design ecosystem is preparing for production programs that require substantially higher bandwidth density than first-generation implementations.
• Open interfaces reduce the cost of reusable and multi-vendor chiplet platforms. Chiplets create the greatest economic advantage when proven dies can be reused across several products rather than redesigned for each system. A standardized interface allows compute, memory, radio-frequency, security or accelerator chiplets to be developed on the process node best suited to each function and connected at package level. AMD is extending this model to selected Versal RF Series devices, where UCIe can connect co-packaged chiplets for radio-frequency conversion, artificial intelligence, central processing units, graphics processing units, security and application-specific functions. Wider adoption can therefore shift UCIe from a connectivity feature into a platform-enablement requirement.
• Interoperability testing is becoming a commercial requirement. A written standard does not guarantee that independently designed chiplets will operate together. PHY behavior, training, sideband signaling, package channels, error handling and protocol mappings must be validated across vendors. The Intel and Cadence live UCIe-S demonstration at Chiplet Summit 2026 was important because it connected independently designed chiplets and validated cross-vendor operation in silicon. As more suppliers enter the ecosystem, design teams will require verification IP, compliance software, test equipment, protocol analysis and structured interoperability programs. This expands revenue beyond the interface IP itself.
• 3D packaging and new application classes expand the implementation envelope. UCIe is extending beyond conventional side-by-side chiplet placement. UCIe 2.0 introduced support for 3D packaging and fine-pitch hybrid-bonding environments. UCIe 3.0 added higher data rates, longer sideband reach and additional manageability features. The consortium is also developing application-specific guidance for automotive systems, where reliability, health monitoring and long product lifecycles are important. These extensions broaden the market for interface IP, verification and test solutions across vertical stacking, automotive compute, optical chiplets and other heterogeneous systems.

Market Restraints

• The principal constraint is that ecosystem readiness develops more slowly than specification capability. A multi-vendor chiplet requires aligned electrical characteristics, package design rules, thermal behavior, security assumptions, test coverage, firmware initialization and supply-chain qualification. Designers may therefore continue using proprietary die-to-die interfaces when they control all dies in a package and value optimization over interoperability. UCIe implementation can also add verification and compliance work before reusable chiplets generate economic benefits. Advanced-package versions depend on fine-pitch assembly and high-yield packaging. Three-dimensional implementations introduce additional thermal and test complexity. Production adoption will therefore be concentrated first in applications where chiplet reuse, external sourcing or platform flexibility justify the integration cost.

Technology and Segment Insights

• Physical-layer and controller IP form the foundation of the commercial UCIe ecosystem because every UCIe-enabled die requires compliant transmit, receive, training and protocol-interface functions. Cadence, Synopsys and Qualcomm through the former Alphawave Semi organization are among the suppliers developing die-to-die connectivity IP for advanced process nodes and package types. Verification IP is closely linked because designers must exercise protocol behavior, link states, lane repair, sideband communication and error conditions before tape-out. Siemens provides UCIe verification IP supporting the die-to-die adapter and logical PHY layers together with PCI Express and Compute Express Link operation over UCIe.
• Compliance, test and package-analysis tools form a separate but increasingly important layer. UCIe performance depends on the combined die and package channel. This requires electrical models, voltage-transfer-function analysis, interoperability testing and silicon characterization. Keysight has incorporated UCIe 3.0 support into its chiplet design environment, including quarter-rate clock measurement and channel modeling. As production designs move toward 64 GT/s and 3D integration, test complexity increases and creates recurring demand for measurement hardware, software and engineering support.
• Artificial intelligence accelerators and high-performance computing processors are the primary near-term applications because they already use multi-die architectures and require extreme bandwidth density. Data-center networking and custom cloud silicon follow for similar reasons, especially where compute, memory, optical input and output or network functions can be developed as reusable chiplets. Client and edge processors are beginning to adopt chiplet approaches at lower cost points. Automotive platforms represent a longer-cycle opportunity that benefits from modular compute and reuse across vehicle programs. Optical and memory chiplets create additional opportunities as system architects move high-bandwidth data movement closer to compute dies.
• The market is segmented by enablement layer, UCIe generation, package type, application, customer type and geography. Enablement layers include UCIe controller and protocol IP, UCIe PHY IP, verification IP, design and package and signal-integrity software, compliance and interoperability test systems, and integration, bring-up and engineering services. UCIe generations include UCIe 1.x implementations, UCIe 2.0 and 3D packaging, UCIe 3.0 48G and 64G implementations, and future specification evolution. Package types include standard package UCIe, advanced package UCIe, 2.5D interposer and bridge packages, and 3D and hybrid-bonded multi-die systems. Applications include AI accelerators and GPUs, high-performance computing and server CPUs, data-center networking and custom cloud silicon, client and edge computing, automotive compute, and optical, memory and specialized chiplets. Customer types include fabless semiconductor companies, integrated device manufacturers, cloud and hyperscale silicon developers, foundries and advanced packaging providers, automotive and industrial semiconductor companies, and IP, EDA and design-service providers.
• UCIe 3.0 raises supported data rates to 48 GT/s and 64 GT/s for next-generation chiplet systems. Cross-vendor interoperability moved from specification goals to live silicon demonstrations during 2026. AI and high-performance computing remain the strongest near-term drivers for production UCIe adoption. Verification, compliance and package co-design become more valuable as multi-vendor chiplet programs expand. Automotive, optical and configurable-compute applications broaden the addressable market beyond data centers.

Competitive and Strategic Outlook

• The competitive landscape combines interface-IP suppliers, electronic design automation vendors, semiconductor companies, foundries, advanced packaging providers and test-equipment companies. Cadence and Synopsys compete most directly in complete UCIe IP subsystems spanning controller, PHY and verification. Siemens participates strongly in verification IP and multi-die design workflows. Qualcomm incorporates high-speed wired connectivity and chiplet technology acquired with Alphawave Semi. Intel has contributed both technology development and interoperability demonstrations.
• Semiconductor and manufacturing companies shape the market even when they do not sell UCIe IP directly. AMD is moving UCIe into configurable compute platforms. Arm, NVIDIA and other architecture or processor companies influence interface requirements for reusable chiplets. TSMC, Samsung and ASE provide the process, package and qualification environments in which UCIe IP must operate. Keysight and other measurement companies participate through channel analysis, electrical validation and compliance tools. Specialized companies such as Eliyan, proteanTecs and VeriSilicon add die-to-die connectivity, monitoring, design and integration capabilities around the broader chiplet ecosystem.
• Competitive differentiation depends on silicon proof, process portability, package support, interoperability and complete design enablement rather than peak data rate alone. Customers need working controller and PHY IP, verification environments, known-good package models, debug visibility and reliable bring-up across process-voltage-temperature conditions. Suppliers able to demonstrate multi-vendor interoperability and support both standard and advanced packaging are better positioned as UCIe moves into production programs.
• North America is the strongest early commercial region for UCIe enablement. The United States contains a dense concentration of processor vendors, cloud companies, design-automation suppliers, interface-IP developers and test-equipment companies. Intel, AMD, NVIDIA, Qualcomm, Google, Microsoft and Meta are represented in the UCIe promoter ecosystem. Cadence, Synopsys, Siemens EDA and Keysight provide core implementation and validation tools. This combination creates demand across the full design cycle, from architecture and IP selection to package co-design, verification, characterization and interoperability testing.
• The region is also important because several early production programs are being driven by U.S.-based semiconductor companies. Intel has demonstrated early UCIe adoption in processor roadmaps and participated in live cross-vendor interoperability testing. AMD announced native UCIe connectivity for selected Versal adaptive system-on-chips. This creates a platform intended to attach specialized third-party or internally developed chiplets. Qualcomm gained additional high-speed connectivity and chiplet capabilities through its acquisition of Alphawave Semi. This strengthens another commercial UCIe-capable supplier within the North American ecosystem.
• Cloud and artificial intelligence infrastructure add a second demand layer. Large hyperscalers increasingly design custom accelerators and infrastructure silicon. Reusable chiplets and open die-to-die connectivity are attractive where internal silicon programs need to combine compute, memory, input and output or security functions. UCIe does not require these companies to buy merchant chiplets immediately. Adoption can begin with internal reusable dies and later expand to multi-vendor sourcing as interoperability matures. This phased path supports demand for commercial IP and design tools before a fully open chiplet marketplace develops.
• Asia Pacific remains essential through semiconductor fabrication, advanced packaging and system manufacturing. TSMC, Samsung and ASE are promoter members and can support UCIe-enabled designs through foundry and packaging ecosystems. Taiwan and South Korea are particularly important for advanced packaging. Japan and Southeast Asia contribute materials, test and assembly capabilities. Europe participates through automotive semiconductor demand, processor architecture, design services and verification technologies. Automotive is likely to become more meaningful as reliability-focused UCIe implementations mature.
• Recent developments confirm accelerating market activity. In August 2026, AMD announced native UCIe 1.1 connectivity for selected Versal RF Series adaptive SoCs, with production chiplets expected in the fourth quarter of 2027. In August 2026, Synopsys detailed its 64G UCIe IP roadmap and tape-outs across advanced 2 nm and 3 nm process technologies for multi-die AI and HPC systems. In July 2026, Samsung Foundry and Cadence expanded their AI design collaboration, including UCIe 64G interface IP within the advanced connectivity portfolio for next-generation 2 nm platforms. In July 2026, the UCIe Consortium expanded automotive ecosystem activity around modular compute, reliability, interoperability and long-lifecycle semiconductor requirements. In March 2026, Intel and Cadence demonstrated the industry's first live UCIe-S cross-vendor interoperability using independently designed 16G UCIe chiplets. In August 2025, the UCIe Consortium released UCIe 3.0 with 48 GT/s and 64 GT/s support, extended sideband reach and enhanced manageability and power features.

Conclusion

• The Universal Chiplet Interconnect Express market is growing rapidly as multi-die architectures become mainstream in AI, HPC and custom silicon. Growth is driven by AI and HPC die-to-die bandwidth requirements, reusable and multi-vendor chiplet platforms, interoperability and compliance requirements and 3D packaging and new application classes. Controller and PHY IP form the foundational enablement layer. Verification, compliance and package-analysis tools are increasingly important. AI accelerators and HPC processors are the primary near-term applications. North America leads early commercial enablement. Asia Pacific remains essential for fabrication and advanced packaging. Multi-vendor integration complexity, competition from proprietary interfaces and advanced packaging cost remain the key restraints. The market is projected to grow from USD 0.40 billion in 2026 to USD 3.40 billion by 2032 at a CAGR of 42.9%.

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TABLE OF CONTENTS

1. Executive Summary

• 1.1. Market Opportunity and Key Findings
• 1.2. UCIe Commercialization Outlook
• 1.3. Open Chiplet Ecosystem Development

2. Market Overview

• 2.1. UCIe Architecture and Role in Multi-Die Systems
• 2.2. Die-to-Die Physical Layer and Adapter Architecture
• 2.3. PCI Express, Compute Express Link and Streaming Protocol Support
• 2.4. Standard Package and Advanced Package Implementations
• 2.5. UCIe 3D and Hybrid-Bonded Architectures
• 2.6. Interoperability, Manageability and Debug

3. Market Size and Forecast, 2026-2032

• 3.1. Global Market Revenue
• 3.2. Commercialization and Production Ramp
• 3.3. UCIe-Enabled Design Program Outlook

4. Market by Enablement Layer

• 4.1. UCIe Controller and Protocol IP
• 4.2. UCIe PHY IP
• 4.3. Verification IP
• 4.4. Design, Package and Signal-Integrity Software
• 4.5. Compliance and Interoperability Test Systems
• 4.6. Integration, Bring-Up and Engineering Services

5. Market by UCIe Generation

• 5.1. UCIe 1.x Implementations
• 5.2. UCIe 2.0 and 3D Packaging
• 5.3. UCIe 3.0 48G and 64G Implementations
• 5.4. Future Specification Evolution

6. Market by Package Type

• 6.1. Standard Package UCIe
• 6.2. Advanced Package UCIe
• 6.3. 2.5D Interposer and Bridge Packages
• 6.4. 3D and Hybrid-Bonded Multi-Die Systems

7. Market by Application

• 7.1. AI Accelerators and GPUs
• 7.2. High-Performance Computing and Server CPUs
• 7.3. Data-Center Networking and Custom Cloud Silicon
• 7.4. Client and Edge Computing
• 7.5. Automotive Compute
• 7.6. Optical, Memory and Specialized Chiplets

8. Market by Customer Type

• 8.1. Fabless Semiconductor Companies
• 8.2. Integrated Device Manufacturers
• 8.3. Cloud and Hyperscale Silicon Developers
• 8.4. Foundries and Advanced Packaging Providers
• 8.5. Automotive and Industrial Semiconductor Companies
• 8.6. IP, EDA and Design-Service Providers

9. Regional Market

• 9.1. North America
  • 9.1.1. United States
  • 9.1.2. Canada
• 9.2. Asia Pacific
  • 9.2.1. Taiwan
  • 9.2.2. South Korea
  • 9.2.3. Japan
  • 9.2.4. China and Southeast Asia
• 9.3. Europe
• 9.4. Rest of World

10. Market Dynamics

• 10.1. Drivers
  • 10.1.1. AI and HPC Die-to-Die Bandwidth Requirements
  • 10.1.2. Reusable and Multi-Vendor Chiplet Platforms
  • 10.1.3. Interoperability and Compliance Requirements
  • 10.1.4. 3D Packaging and New Application Classes
• 10.2. Restraints
  • 10.2.1. Multi-Vendor Integration and Qualification Complexity
  • 10.2.2. Competition from Proprietary Die-to-Die Interfaces
  • 10.2.3. Advanced Packaging Yield and Cost
  • 10.2.4. Production Adoption Lag versus Specification Development

11. Competitive Landscape

• 11.1. Market Structure and Commercial Readiness
• 11.2. Controller and PHY IP Competition
• 11.3. Verification and Multi-Die Design Platforms
• 11.4. Compliance, Test and Interoperability Ecosystem
• 11.5. Foundry and Advanced Packaging Partnerships

12. Company Profiles

• 12.1. Cadence Design Systems
• 12.2. Synopsys
• 12.3. Siemens EDA
• 12.4. Intel
• 12.5. AMD
• 12.6. Qualcomm
• 12.7. Arm
• 12.8. NVIDIA
• 12.9. Taiwan Semiconductor Manufacturing Company
• 12.10. Samsung Electronics
• 12.11. ASE Technology Holding
• 12.12. Keysight Technologies
• 12.13. Eliyan
• 12.14. proteanTecs
• 12.15. VeriSilicon

13. Recent Developments

14. Appendix